The present invention is in the field of memory architecture and management. More particularly, the present invention provides a method, apparatus, system, and machine-readable medium to hide refresh cycles of a memory array.
The current trend of processor has been to include more memory hierarchy on-chip to reduce average latency and to satisfy bandwidth requirements. Traditionally on-chip caches are implemented with static random access memory (SRAM) rather than dynamic access memory (DRAM). However, each SRAM cell consists of six transistors, consuming a significant amount of semiconductor area whereas each DRAM cell may comprise a single access transistor coupled to a capacitor to store charge. Thus, DRAM may consume less area for the same amount of data storage.
Using logic DRAM or embedded DRAM to implement on-chip caches, for instance, can be a good alternative from the standpoint of memory density, but DRAM cells need to be refreshed periodically, postponing access to the DRAM. Postponing access during refresh cycles may result in variable latencies, increasing the complexity of a memory or cache interface. For example, a processor may require additional interface circuitry to receive an indication when an access may be performed or to retry requests for access of a DRAM device. Therefore, SRAM is used in conjunction with DRAM to alleviate some of the complexity of memory interfacing while compromising on memory density.